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a s 111 5 6 4 l e d s , i 2c i n t e r f a c e d l e d dr i v e r w i th k e y s c a n www.austriamicrosystems.com/leddriverics/as1115 r e vision 1.08 1 25 d atas h eet 1 general description the as1115 is a compact led driver for 64 single leds or 8 digits of 7 segments. the devices can be programmed via an i2c compatible 2wire interface. every segment can be individually addressed and updated sepa rately. only one external resistor (r set ) is required to set the cur re nt. led brightness can be controlled by analog or digital means. the devices include an integrated bcd codeb/hex decoder, multi plex scan circuitry, segment and display drivers, and a 64bit mem ory. internal memory stores the shift register settings, eliminating the need for continuous device reprogramming. all outputs of the as1115 can be configured for key readback. key switch status is obtained by polling for up to 64 keys while 16 keys can be used to trigger an interrupt. additionally the as1115 offers a diagnostic mode for easy and fast production testing. the as1115 features a low shutdown current of typically 200na, and an operational current of typically 350a. the number of digits can be programmed, the devices can be reset by software, and an exter nal clock is also supported. the device is available in a qsop24 and the tqfn(4x4)24 pack age. figure 1. as1115 - typical application diagram 2 key features up to 1mhz i2ccompatible interface individual led segment control readback for 16 keys plus interrupt open and shorted led error detection global or individual error detection hexadecimal or bcdcode for 7segment displays 200na lowpower shutdown current (typ; data retained) digital and analog brightness control display blanked on powerup drive commoncathode led displays supply voltage range: 2.7 to 5.5v software reset optional external clock package: q sop24 tqfn(4x4)24 3 applications the as1115 is ideal for sevensegment or dot matrix user interface d i splays of settop boxes, vcrs, dvdplayers, washing machines, micro wave ovens, refrigerators and other white good or personal electronic applications. as1115 dig0 to dig7 sega-dp key0-7 8 sda scl irq v dd iset sda irq gnd scl 2.7 to 5.5v 9.53k w p 8 keya keyb 8 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 2 25 as1115 datasheet p i n o u t 4 pinout pi n assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions pin name qsop-24 tqfn(4x4)-24 description sda 1 22 serial-data i/o . open drain digital i/o i2c data pin. dig0:dig7 25, 710 1, 2, 4, 5, 6, 7, 23, 24 digit drive lines . eight digit drive lines that sink current from the display common cathode. keyscan detection optional, but must be polled by the prozessor. gnd 6 3 ground . keya 11 8 keyscan input. keyscan lines for key readback. can be used for selfaddressing. keyb 12 9 keyscan input. keyscan lines for key readback. iset 13 10 set segment current . connect to v dd or a reference voltage through r set to set the p e ak segment current (see selecting rset resistor value and using external dri vers on page 19 ). scl 1 4 11 serial-clock input . 3.4mhz maximum rate. irq 24 21 interupt request output . open drain pin. sega:segg, segdp 1518, 2023 1215, 1720 seven segment and decimal point drive lines . 8 sevensegment drives and decimal point drive that source current to the display. vdd 19 16 positive supply voltage . connect to +2.7 to +5.5v supply. exposed pad exposed pad. this pin also functions as a heat sink. solder it to a large pad or to the circuitboard ground plane to maximize power dissipation. 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 irq segd segdp seg e segc vdd segg segb segf sega scl iset sda dig0 dig1 dig2 dig3 gnd dig4 dig5 dig6 dig7 keya keyb as1115 seg e keya 8 18 segb 14 dig2 1 gnd 3 as1115 dig5 5 iset 10 sega 12 vdd 16 segc 17 segg 15 segf 13 dig3 2 dig4 4 dig6 6 scl 11 keyb 9 dig7 7 dig0 23 irq 21 segdp 19 segd 20 sda 22 dig1 24 exposed pad ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 3 25 as1115 datasheet a b s o l u t e m a x i m u m r a t i n g s 5 absolute maximum ratings stresses beyond those listed in ta ble 2 may cause permanent damage to the device. these are s tress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. exp osure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters vdd to gnd 0.3 7 v all other pins to gnd 0.3 7 or v dd + 0.3 v di g0:dig7 sink current 500 ma sega:segg, segdp sink current 100 ma input current (latchup immunity) 100 100 ma norm: jedec 78 electrostatic discharge electrostatic discharge hbm +/ 1 kv norm: mil 883 e method 3015 thermal information thermal resistance q ja 88 c/w on pcb, qsop24 package 30.5 c/w on pcb, tqfn(4x4)24 package temperature ranges and storage conditions junction temperature +150 oc storage temperature range 55 +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std- 020moisture/reflow sensitivity classification for non- hermetic solid state surface mount devices. the lead finish for pbfree leaded packages is matte tin (100% sn). humidity noncondensing 5 85 % moisture sensitive level 1 represents a max. floor life time of unlimited ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 4 25 as1115 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s 6 electrical characteristics v dd = 2.7v to 5.5v, r set = 9.53k w , typ. values @ t amb = +25oc, v dd = 5.0v (unless otherwise specified). all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. table 3. electrical characteristics symbol parameter conditions min typ max unit t amb operating temperature range 4 0 +85 c t j operating junction temperature range 4 0 +125 c v dd operating supply voltage 2. 7 5.5 v i ddsd shutdown supply current al l digital inputs at v dd or gnd, t amb = +25oc 0. 2 2 a single digit, t amb = +85oc 4 a i dd operating supply current r set = open circuit. 0. 35 0.6 ma all segments and decimal point on; i seg = 40ma. 33 5 f osc display scan rate 8 digits scanned 0.48 0.96 khz i digit digit drive sink current v out = 0.65v 32 0 ma i seg segment drive source current v dd = 5.0v, v out = (v dd 1v) 3 5 41 47 ma d i seg segment drive current matching 3 % i s eg segment drive source current average current 47 ma table 4. logic inputs/outputs characteristics symbol parameter conditions min typ max unit i ih , i il input current sda, scl v in = 0v or v dd 1 1 a v ih logic high input voltage sda, scl 0. 7xv dd v v il logic low input voltage sda, scl 0. 3xv dd v v ol(sda) sda output low voltage i sink = 3ma 0. 4 v v keyopen keyscan open input voltage 0. 8xv dd v v keyshort keyscan short input voltage 0. 7x v dd v v ol(irq) interrupt output low voltage i sink = 3ma 0. 4 v d v i hysteresis voltage di n, clk, ld/cs 1 v c b capacitive load for each bus line 550 pf open detection level threshold 0.7x v dd 0.75x v dd 0.8x v dd v sh ort detection level threshold 0.05x v dd 0.1x v dd 0.15x v dd v ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 5 25 as1115 datasheet e l e c t r i c a l c h a r a c t e r i s t i c s note: t he min / max values of the timing characteristics are guaranteed by design. f igure 3. timing diagram table 5. timing characteristics (c b = 550pf (max) on each bus line) symbol parameter conditions min typ max unit f scl scl frequency 1 m hz t buf bus free time between stop and start co nditions 500 ns t holdstart hold time for repeated st art condition 260 ns t low scl low period 5 0 0 ns t high scl high period 26 0 ns t setupstart setup time for repeated st art condition 260 ns t setupdata data setup time 50 n s t rise sda + scl rise time 12 0 ns t fall sda + scl fall time 12 0 ns t setupstop stop condition setup time 26 0 ns t spikesup pulse width of spike suppressed 50 n s key readback debounce time 20 ms repeated start sdi scl start stop t buf t low t holdstart t holddata t r t high t f t setupdata t holdstart t spikesup t setupstop t setupstart ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 6 25 as1115 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s 7 typical operating characteristics r set = 9.53k w, v r set = v dd ; fi gure 4. display scan rate vs. supply voltage; figure 5. display scan rate vs. temperature; 680 700 720 740 760 780 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 vdd (v) fosc (hz) . tamb=-40c tamb=+25c tamb=+85c 680 700 720 740 760 780 800 -40 -15 10 35 60 85 tamb (c) fosc (hz) . vdd=2.7v vdd=4v vdd=5v vdd=5.5v figure 6. segment current vs. temperature; figure 7. segment current vs. r set ; 0 10 20 30 40 50 60 -40 -15 10 35 60 85 tamb (c) iseg (ma) . vseg = 1.7v; vdd = 2.7v vseg = 1.7v; vdd = 5v vseg = 3v; vdd = 5v vseg = 4v; vdd = 5v 0 10 20 30 40 50 0 10 20 30 40 50 60 70 80 90 rset (kohm) iseg (ma) . vseg = 4v; vdd = 5v vseg = 3v; vdd = 5v vseg = 2v; vdd = 5v vseg = 1.7v; vdd = 2.7v figure 8. segment current vs. supply voltage; figure 9. segment current vs. v dd ; v rset = 2.8v 0 10 20 30 40 50 60 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 vdd (v) iseg (ma) . vseg = 1.7v vseg = 3v vseg = 4v 0 5 10 15 20 25 30 35 40 45 50 2.7 3 3.3 3.6 3.9 4.2 vdd (v) iseg (ma) . vseg = 1.7v vseg = 2v vseg = 2.3v vseg = 3.1v ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 7 25 as1115 datasheet ty p i c a l o p e r a t i n g c h a r a c t e r i s t i c s figure 10. v digit vs. i digit figure 11. input high level vs. supply voltage 0 0.1 0.2 0.3 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 idig (a) vdig (v) . vdd = 2.7v vdd = 3.3v vdd = 4v vdd = 5v vdd = 5.5v 0 0.5 1 1.5 2 2.5 3 3.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 vdd (v) vih (v) . figure 12. i seg vs. v seg ; v dd = 5v fi gure 13. i seg vs. v seg ; v dd = 4v 0 5 10 15 20 25 30 35 40 45 50 2 2.5 3 3.5 4 4.5 5 vseg (v) iseg (ma) . rext = 10k rext = 13k rext = 18k rext = 30k rext = 56k 0 5 10 15 20 25 30 35 40 45 50 1 1.5 2 2.5 3 3.5 4 vseg (v) iseg (ma) . rext = 8k2 rext = 10k rext = 13k rext = 18k rext = 30k figure 14. i seg vs. v seg ; v dd = 3.3v fi gure 15. i seg vs. v seg ; v dd = 2.7v 0 5 10 15 20 25 30 35 40 45 50 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 vseg (v) iseg (ma) . rext = 6k8 rext = 8k2 rext = 10k rext = 13k rext = 18k 0 5 10 15 20 25 30 35 40 45 50 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vseg (v) iseg (ma) . rext = 4k7 rext = 5k6 rext = 6k8 rext = 10k rext = 13k ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 8 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n 8 detailed description bl ock diagram figure 16. as1115 - block diagram (qsop-24 package) f i gure 17. esd structure as1115 registers digital control logic oszillator open/short detection i2c interface + C + C 19 vdd scan - registers control - registers data - registers (pwm, debounce,....) r set 13 iset 15-18, 20-23 sega-g, segdp 2-5, 7-10 dig0 to dig7 6 gnd vdd 11, 12 keya, keyb 8 8 2 vdd vdd vdd 1 sda 14 scl 24 irq vdd valid for the pins: - irq - scl - sda - iset - sega-g, segdp - keya, keyb vdd valid for the pins: - dig0 to dig7 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 9 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n i2c interface the as1115 supports the i2c serial bus and data transmission protocol in highspeed mode at 3.4mhz. the as1115 operates as a slave on the i2 c bus. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. connections to the bus are made via the opendrain i/o pins scl and sda. figure 18. i2c interface initialization figure 19. bus protocol the bus protocol (as shown in figure 19 ) is defined as: d a ta transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. the bus conditions are defined as: bus not busy . data and clock lines remain high. start data transfer . a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfe r. a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid . the state of the data line represents valid data, when, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred bytewise and each receiver acknowledges with a ninthbit. within the i2c bus specifications a highspeed mode (3.4mhz clock rate) is defined. acknowledge : each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the mas ter device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generat 1 98 1 98 0 0 0 0 0 a1 a0 r/w d15 d14 d13 d12 d11 d10 d9 d8 default values at power up: a1 = a0 = 0 sdi scl slave address r/w direction bit start 1 2 6 7 8 9 1 2 3-8 8 9 ack msb repeat if more bytes transferred stop or repeated start ack from receiver ack from receiver ack ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 10 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n ing an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to en able the master to generate the stop condition. figure 19 on page 9 details how data transfer is accomplished on the i2c bus. depending upon the state of the r/w bit, two types of data transfer are possible: master transmitter to slave receiver . the first byte transmitted by the master is the slave address, followed by a number of data bytes. the slave returns an acknowledge bit after the slave address and each received byte. slave transmitter to master receiver . the first byte, the slave address, is transmitted by the master. the slave then returns an acknowl edge bit. next, a number of data bytes are transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a notacknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the as1115 can operate in the following slave modes: slave receiver mode . serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is trans mitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. slave transmitter mode . the first byte (the slave address) is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the as1115 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. i2c device address byte the address byte ( s ee figure 20) is the first byte received following the start condit ion from the master device. figure 20. i2c device address byte the default slave address is factoryset to 0000000. the two lsb bits of the address byte are the device select bits, a0 to a1, which can be set by the self address command after startup. a maximum of four devices with the same preset code can therefore be connected on the same bus at one time. a short writes a logical 0 whereas an open writes a logical 1 as address bit ( see figure 26 on page 15 ). t h e last bit of the address byte (r/w ) define the operation to be performed. when set to a 1 a read operation is selected; when set to a 0 a write operation is selected. following the start condition, the as1115 monitors the i2c bus, checking the device type identifier being transmitted. upon receiving the address code, and the r/w bit, the slave device outputs an acknowledge signal on the sda line. i2c device self addressing if this feature is used, 2 of the 16 key readback nodes can be left open or shorted for selfaddressing. this is done with keya together with se gg (a0) and segf (a1). this two nodes cannot be used for keyreadback in this case. after startup all devices have the predefined address 0000000. a single command for self addressing will update all connected as1115. this command has to be done after startup or every time the as1115 gets disconnected from the supply. the i2c address definition must be done with fixed connection, since i2c detection is excluded from debounce time of key registers. 0 0 0 0 0 0 0 r/w msb 6 5 4 3 2 1 lsb 0 0 0 0 0 a1 a0 r/w msb 6 5 4 3 2 1 lsb predefined address: up dated address: ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 11 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n command byte the as1115 operation, (see table 6) is determined by a command byte ( se e figure 21 on page 11 ). fig ure 21. command byte figure 22. command and single data byte received figure 23. setting the pointer to a address register to select a data register for a read operation figure 24. reading nbytes from as1115 d15 d14 d13 d12 d11 d10 d09 d08 msb 6 5 4 3 2 1 lsb from master to slave from slave to master a a p a s command byte data byte slave address d14 d13 d12 d11 d10 d9 d8 d15 d6 d5 d4 d3 d2 d1 d0 d7 acknowledge from as1115 0 0 0 acknowledge from as1115 acknowledge from as1115 r/w 0 as1115 registers autoincrement memory word address 1 byte from master to slave from slave to master a p a s command byte slave address d14 d13 d12 d11 d10 d9 d8 d15 0 0 acknowledge from as1115 acknowledge from as1115 r/w 0 as1115 registers from master to slave from slave to master a /a p a s first data byte second data byte slave address d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 not acknowledge from master 0 1 0 acknowledge from master acknowledge from as1115 r/w 1 as1115 registers auto increment memory word address n bytes auto increment to next address stop reading ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 12 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n initial power-up on initial powerup, the as1115 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. at th is time, all registers should be programmed for normal operation. note: the default settings enable only scanning of one digit; the internal decoder is disabled and the intensity control register ( see page 17 ) is set to the minimum values. shutdown mode the as1115 devices feature a shutdown mode, where they consume only 200na (typ) current. shutdown mode is entered via a write to the shut d o wn register (see table 7 ). during shutdown mode the digitregisters maintain t heir data. shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leav ing shutdown mode). for minimum supply current in shutdown mode, logic input should be at gnd or v dd (cmos logic level). wh en entering or leaving shutdown mode, the feature register is reset to its default values (all 0s) when shutdown register bit d7 (page 13) = 0. note: when shutdown register bit d7 = 1, the feature register is left unchanged when entering or leaving shutdown mode. if the as1115 is used with an external clock, shutdown register bit d7 should be set to 1 when writing to the shutdown register. digit- and control-registers the as1115 devices contain 8 digitregisters,11 controlregisters and 10 diagnosticregisters, which are listed in ta ble 6 . all registers are sel ected using a 8bit address word, and communication is done via the i2c interface. digit registers C these registers are realized with an onchip 64bit memory. each digit can be controlled directly without rewriting the wh ole register contents. control registers C these registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and fea tu res selection registers. table 6. register address map type register address page d15:d13 d12 d11 d10 d9 d8 d7:d0 digit register digit 0 000 0 0 0 0 1 (see table 9 on page 14 , table 10 on page 14 and table 11 on page 15 ) n/a d igit 1 000 0 0 0 1 0 n/a digit 2 000 0 0 0 1 1 n/a digit 3 000 0 0 1 0 0 n/a digit 4 000 0 0 1 0 1 n/a digit 5 000 0 0 1 1 0 n/a digit 6 000 0 0 1 1 1 n/a digit 7 000 0 1 0 0 0 n/a control register decodemode 000 0 1 0 0 1 ( see table 8 on page 13 ) 13 global intensity 000 0 1 0 1 0 ( see table 17 on page 17 ) 17 scan limit 000 0 1 0 1 1 ( see table 19 on page 17 ) 17 shutdown 000 0 1 1 0 0 ( see table 7 on page 13 ) 12 self addressing 001 0 1 1 0 1 n/a f eature 000 0 1 1 1 0 ( see table 20 on page 18 ) 18 display test mode 000 0 1 1 1 1 ( see table 14 on page 16 ) 13 dig0:dig1 intensity 000 1 0 0 0 0 ( see table 18 on page 17 ) dig 2:dig3 intensity 000 1 0 0 0 1 ( see table 18 on page 17 ) di g 4:dig5 intensity 000 1 0 0 1 0 ( see table 18 on page 17 ) dig 6:dig7 intensity 000 1 0 0 1 1 ( see table 18 on page 17 ) ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 13 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n the shutdown register controls as1115 shutdown mode. decode enable register (0x09) the decode enable register sets the decode mode. bcd/hex decoding (either bcd code C characters 0:9, e, h, l, p, and , or hex code C c h aracters 0:9 and a:f) is selected by bit d2 (page 18) of the feature register. the decode enable register is used to select the decode mode or nodecode for each digit. each bit in the decode enable register corresponds to its respective display digit (i.e., bit d0 corresponds to digit 0, bit d1 corresponds to digit 1 and so on). table 9 lists some examples of the possible settings for the decode enable register bits. note: a logic high enables decoding and a logic low bypasses the decoder altogether. when decode mode is used, the decoder looks only at the lowernibble (bits d3:d0) of the data in the digitregisters, disregarding bits d6:d4. bit d7 sets the decimal point (seg dp) independent of the decoder and is positive logic (bit d7 = 1 turns the decimal point on). table 9 lists the cod eb font; table 10 lists the hex font. whe n nodecode mode is selected, data bits d7:d0 of the digitregisters correspond to the segment lines of the as1115. table 11 shows the 1:1 pairing of each data bit to the appropriate segment line. keyscan/diagnostic register diagnostic digit 0 000 1 0 1 0 0 n/a diagnostic digit 1 000 1 0 1 0 1 n/a diagnostic digit 2 000 1 0 1 1 0 n/a diagnostic digit 3 000 1 0 1 1 1 n/a diagnostic digit 4 000 1 1 0 0 0 n/a diagnostic digit 5 000 1 1 0 0 1 n/a diagnostic digit 6 000 1 1 0 1 0 n/a diagnostic digit 7 000 1 1 0 1 1 n/a keya 000 1 1 1 0 0 keyb 000 1 1 1 0 1 table 7. shutdown register format (address (hex) = 0x0c)) mode hex code register data d7 d6 d5 d4 d3 d2 d1 d0 shutdown mode, reset feature register to default settings 0x00 0 x x x x x x 0 shutdown mode, feature register unchanged 0x80 1 x x x x x x 0 normal operation, reset feature register to default settings 0x01 0 x x x x x x 1 normal operation, feature register unchanged 0x81 1 x x x x x x 1 table 8. decode enable register format examples decode mode hex code register data d7 d6 d5 d4 d3 d2 d1 d0 no decode for digits 7:0 0x00 0 0 0 0 0 0 0 0 codeb/hex decode for digit 0. no decode for digits 7:1 0x01 0 0 0 0 0 0 0 1 codeb/hex decode for digit 0:2. no decode for digits 7:3 0x07 0 0 0 0 0 1 1 1 codeb/hex decode for digits 0:5. no decode for digits 7:6 0x3f 0 0 1 1 1 1 1 1 codeb/hex decode for digits 0,2,5. no decode for digits 1, 3, 4, 6, 7 0x25 0 0 1 0 0 1 0 1 table 6. register address map type register address page d15:d13 d12 d11 d10 d9 d8 d7:d0 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 14 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n figure 25. standard 7-segment led intensity control and inter-digit blanking ta ble 9. code-b font char- acter register data char- acter register data char- acter register data d7 d6:d4 d3 d2 d1 d0 d7 d6: d4 d3 d2 d1 d0 d7 d6:d4 d3 d2 d1 d0 x 0 0 0 0 x 0 1 1 0 x 1 1 0 0 x 0 0 0 1 x 0 1 1 1 x 1 1 0 1 x 0 0 1 0 x 1 0 0 0 x 1 1 1 0 x 0 0 1 1 x 1 0 0 1 x 1 1 1 1 x 0 1 0 0 x 1 0 1 0 1 * x x x x x x 0 1 0 1 x 1 0 1 1 * the decimal point can be enabled with every character by setting bit d7 = 1. table 10. hex font char- acter register data char- acter register data char- acter register data d7 d6:d4 d3 d2 d1 d0 d7 d6: d4 d3 d2 d1 d0 d7 d6:d4 d3 d2 d1 d0 x 0 0 0 0 x 0 1 1 0 x 1 1 0 0 x 0 0 0 1 x 0 1 1 1 x 1 1 0 1 x 0 0 1 0 x 1 0 0 0 x 1 1 1 0 x 0 0 1 1 x 1 0 0 1 x 1 1 1 1 x 0 1 0 0 x 1 0 1 0 1 * x x x x x x 0 1 0 1 x 1 0 1 1 * the decimal point can be enabled with every character by setting bit d7 = 1. a b g f e d c dp ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 15 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n i2c self addressing if this feature is used, 2 of the 16 key readback nodes can be left open or shorted for selfaddressing. this is done with keya together with se gg (a0) and segf (a1). this two nodes cannot be used for keyreadback in this case. after startup all devices have the predefined address 0000000. a single command for self addressing will update all connected as1115. this command has to be done after startup or every time the as1115 gets disconnected from the supply. the i2c address definition must be done with fixed connection, since i2c detection is excluded from debounce time of key registers.geht note: a short writes a logical 0 whereas an open writes a logical 1 as address bit (see figure 26) . fi g ure 26. address coding keyscan register these two registers contain the result of the keyscan input of the 16 keys. to ensure proper results the data in these registers are updated only i f the logic data scanned is stable for 20ms (debounce time). a change of the data stored within these two registers is indicated by a logic low on the irq pin. the irq is highimpedance if a read operation on the key scan registers is started. note: if i2c self addressing is used segment g&f of keya is used for the two lsb of the i2c address. in this case these two nodes cannot be used as a key. additionally the debounce time is disabled for these two bits. the data within the keyscan register is updated continuously during every cycle (1/10 of refresh rate). therefore, to get a valid read back of keys it is recommended to read out the keyscan registers immediately after the irq is triggered. a short writes a logical 0 whereas an open writes a logical 1 as keyscan register bit. note: if the blink_en bit (bit d4 in the feature register 0x0e) is set to 1, the keyscan is not returning a valid value. table 11. no-decode mode data bits and corresponding segment lines d7 d6 d5 d4 d3 d2 d1 d0 corresponding segment line dp a b c d e f g table 12. self addressing register (address (hex) = 0x2d)) d7 d6 d5 d4 d3 d2 d1 d0 factoryset ic address x x x x x x x 0 userset ic address x x x x x x x 1 table 13. led diagnostic register address register hex address segment key d7 d6 d5 d4 d3 d2 d1 d0 0x1c keya dp a b c d e f g 0x1d keyb ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 16 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n display-test mode the as1115 can detect open or shorted leds. readout of either open leds or short leds is possible, as well as a or relation of open and sh ort. note: all settings of the digit and controlregisters are maintained. led diagnostic registers these eight registers contain the result of the led open/short test for the individual led of each digit. n o te: if one or more short occures in the led array, detection of individual led fault could become ambiguous. intensity control register (0x0a) the brightness of the display can be controlled by digital means using the intensity control registers and by analog means using r set (see se lecting rset resistor value and using external drive rs on page 19 ). the intensity can be controlled globally for all di gits, or for each digit individually. the global intensity command will write intensity data to all four individual brightness registers, while the individual intensity command will only write to the associated individual intensity register. table 14. testmode register summary d7 d6 d5 d4 d3 d2 d1 d0 x rset_short rset_open led_global led_test led_open led_short disp_test table 15. testmode register bit description (address (hex) = 0x0f)) addr: 0x0f address bit bit name default access d7:d0 d0 disp_test 0 w optical display test. (testmode for external visual test.) 0: normal operation; 1: run display test (all digits are tested independently from scan limit & shutdown register.) d1 led_short 0 w starts a test for shorted leds. (can be set together with d2) 0: normal operation; 1: activate testmode d2 led_open 0 w starts a test for open leds. (can be set together with d1) 0: normal operation; 1: activate testmode d3 led_test 0 r indicates an ongoing open/short led test 0: no ongoing led test; 1: led test in progress d4 led_global 0 r indicates that the last open/short led test has detected an error 0: no error detected; 1: error detected d5 rset_open 0 r checks if external resistor r set is open 0: r set correct; 1: r set is open d6 rset_short 0 r checks if external resistor r set is shorted 0: r set correct; 1: r set is shorted d 7 0 not used table 16. led diagnostic register address register hex address segment register hex address segment digit d7 d6 d5 d4 d3 d2 d1 d0 digit d7 d6 d5 d4 d3 d2 d1 d0 0x14 dig0 dp a b c d e f g 0x18 dig4 dp a b c d e f g 0x15 dig1 0x19 dig5 0x16 dig2 0x1a dig6 0x17 dig3 0x1b dig7 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 17 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n display brightness is controlled by an integrated pulsewidth modulator which is controlled by the lowernibble of the intensity control register. th e modulator scales the average segmentcurrent in 16 steps from a maximum of 15/16 down to 1/16 of the peak current set by r set . scan-limit register (0x0b) the scanlimit register controls which of the digits are to be displayed. when all 8 digits are to be displayed, the update frequency is typically 7 0 0hz. if the number of digits displayed is reduced, the update frequency is increased. the frequency can be calculated using 10 x fosc/(n+2), where n is the number of digits. note: to avoid differences in brightness this register should not be used to blank parts of the display (leading zeros). table 17. intensity register format duty cycle hex code register data duty cycle hex code register data msb d2 d1 lsb msb d2 d1 lsb 1/16 (min on) 0xx0 0 0 0 0 9/16 0xx8 1 0 0 0 2/16 0xx1 0 0 0 1 10/16 0xx9 1 0 0 1 3/16 0xx2 0 0 1 0 11/16 0xxa 1 0 1 0 4/16 0xx3 0 0 1 1 12/16 0xxb 1 0 1 1 5/16 0xx4 0 1 0 0 13/16 0xxc 1 1 0 0 6/16 0xx5 0 1 0 1 14/16 0xxd 1 1 0 1 7/16 0xx6 0 1 1 0 15/16 0xxe 1 1 1 0 8/16 0xx7 0 1 1 1 15/16 (max on) 0xxf 1 1 1 1 table 18. intensity register address register hex address register data type d7:d4 d3:d0 0x0a global x global intensity 0x10 digit digit 1 intensity digit 0 intensity 0x11 digit digit 3 intensity digit 2 intensity 0x12 digit digit 5 intensity digit 4 intensity 0x13 digit digit 7 intensity digit 6 intensity table 19. scan-limit register format (address (hex) = 0x0b)) scan limit hex code register data scan limit hex code register data d7:d3 d2 d1 d0 d7:d3 d2 d1 d0 display digit 0 only 0xx0 x 0 0 0 display digits 0:4 0xx4 x 1 0 0 display digits 0:1 0xx1 x 0 0 1 display digits 0:5 0xx5 x 1 0 1 display digits 0:2 0xx2 x 0 1 0 display digits 0:6 0xx6 x 1 1 0 display digits 0:3 0xx3 x 0 1 1 display digits 0:7 0xx7 x 1 1 1 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 18 25 as1115 datasheet d e t a i l e d d e s c r i p t i o n feature register (0x0e) the feature register is used for enabling various features including switching the device into external clock mode, applying an external reset, se lecting codeb or hex decoding, enabling or disabling blinking, setting the blinking rate, and resetting the blink timing. note: at powerup the feature register is initialized to 0. table 20. feature register summary d7 d6 d5 d4 d3 d2 d1 d0 blink_ start sync blink_ freq_sel blink_en nu decode_sel reg_res clk_en table 21. feature register bit descriptions (address (hex) = 0xxe) addr: 0xxe feature register enables and disables various device features. bit bit name default access bit description d0 clk_en 0 r/w external clock active. 0 = internal oscillator is used for system clock. 1 = pin clk of the serial interface operates as system clock input. d1 reg_res 0 r/w resets all control registers except the feature register. 0 = reset disabled. normal operation. 1 = all control registers are reset to default state (except the feature register) identically after powerup. note: the digit registers maintain their data. d2 decode_sel 0 r/w selects display decoding for the selected digits ( table 8 on page 13 ). 0 = enable codeb decoding (see table 9 on page 14 ). 1 = enable hex decoding (see table 10 on page 14 ). d3 n u not used d4 blink_en 0 r/w enables blinking. 0 = disable blinking. 1 = enable blinking. d5 blink_freq_sel 0 r/w sets blink with low frequency (with the internal oscillator enabled): 0 = blink period typically is 1 second (0.5s on, 0.5s off). 1 = blink period is 2 seconds (1s on, 1s off). d6 sync 0 r/w synchronizes blinking on the rising edge of pin ld/cs. the multiplex and blink timing counter is cleared on the rising edge of pin ld/cs. by setting this bit in multiple devices, the blink timing can be synchronized across all the devices. d7 blink_start 0 r/w start blinking with display enabled phase. when bit d4 (blink_en) is set, bit d7 determines how blinking starts. 0 = blinking starts with the display turned off. 1 = blinking starts with the display turned on. ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 19 25 as1115 datasheet ty p i c a l a p p l i c a t i o n 9 typical application se lecting r set resistor value and using external drivers brightness of the display segments is controlled via r set . the current that flows into i set defines the current that flows through the leds. se gment current is about 200 times the current in i set . typical values for r set for different segment currents, operating voltages, and led volt ag e drop (v led ) are given in ta ble 22 & table 23 . the maximum current the as1115 can drive is 47ma. if higher currents are needed, exter nal drivers must be used, in which case it is no longer necessary that the devices drive high currents. note: the display brightness can also be logically controlled (see intensity control register (0x0a) on page 16) . calculating power dissipation the upper limit for power dissipation (pd) for the as1115 is determined from the following equation: p d = (v dd x 5ma) + (v dd - v led )(duty x i seg x n) (e q 1) where: v dd is the supply voltage. du ty is the duty cycle set by intensity register (page 17) . n is the number of segments driven (worst case is 8) v led is the led forward voltage i seg = segment current set by rset di ssipation example: i seg = 40ma, n = 8, duty = 15/16, v led = 2.2v at 40ma, v dd = 5v (e q 2) pd = 5v(5ma) + (5v - 2.2v)(15/16 x 40ma x 8) = 0.865w (eq 3) thus, for a tqfn(4x4)24 package * ja = +30.5c/w, the maximum allowed t amb is given by: t j,max = t amb + pd x q ja = 150c = t amb + 0.865w x 30.5c/w (e q 4) in this example the maximum ambient temperature must stay below 123.61c. table 22. r set vs. segment current and led forward voltage, v dd = 2.7v & 3.3v & 3.6v i seg (ma) v led v led v led 1.5v 2.0v 1.5v 2.0v 2.5v 1.5v 2.0v 2.5v 3.0v 40 v dd = 2.7v 5k ? 4.4k ? v dd = 3.3v 6.7k ? 6.4k ? 5.7k ? v dd = 3.6v 7.5k ? 7.2k ? 6.6k ? 5.5k ? 30 6.9k ? 5.9k ? 9.1k ? 8.8k ? 8.1k ? 10.18k ? 9.8k ? 9.2k ? 7.5k ? 20 10.7k ? 9.6k ? 13.9k ? 13.3k ? 12.6k ? 15.6k ? 15k ? 14.3k ? 13k ? 10 22.2k ? 20.7k ? 28.8k ? 27.7k ? 26k ? 31.9k ? 31k ? 29.5k ? 27.3k ? table 23. r set vs. segment current and led forward voltage, v dd = 4.0v & 5.0v i seg (ma) v led v led 1.5v 2.0v 2.5v 3.0v 3.5v 1.5v 2.0v 2.5v 3.0v 3.5v 4.0v 40 v dd = 4.0v 8.6k ? 8.3k ? 7.9k ? 7.6k ? 5.2k ? v dd = 5.0v 11.35k ? 11.12k ? 10.84k ? 10.49k ? 10.2k ? 9.9k ? 30 11.6k ? 11.2k ? 10.8k ? 9.9k ? 7.8k ? 15.4k ? 15.1k ? 14.7k ? 14.4k ? 13.6k ? 13.1k ? 20 17.7k ? 17.3k ? 16.6k ? 15.6k ? 13.6k ? 23.6k ? 23.1k ? 22.6k ? 22k ? 21.1k ? 20.2k ? 10 36.89k ? 35.7k ? 34.5k ? 32.5k ? 29.1k ? 48.9k ? 47.8k ? 46.9k ? 45.4k ? 43.8k ? 42k ? ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 20 25 as1115 datasheet ty p i c a l a p p l i c a t i o n 8x8 dot matrix mode the application example in fi gure 27 shows the as1115 in the 8x8 led dot matrix mode. the led columns have common cathodes and are connected to the dig0:7 outputs. the rows are connected to the segment drivers. each of the 64 leds can be addressed separately. the columns are selected via the digits as listed in table 6 on page 12 . the decode enable register ( see page 13 ) must be set to 00000000 as described in table 8 on page 13 . single leds in a column can be addressed as described in table 11 on page 15 , where bit d0 corresponds to segment g and bit d7 cor responds to segment dp. figure 27. application example as led dot matrix driver keyscan the key readback of the as1115 can be used either for push buttons as well as switches. if only a single key is pressed (shorted) at a time no a d ditional diodes are required. if a detection of multiple simultaneous keystrokes is required diodes within the keypath, as shown in figure 28 , are required. pressing multiple keys without the diodes would result in ambiguous results. since keya and keyb have independent inputs only keys on the same path are affected. figure 28. keyscan configuration note: if the blink_en bit (bit d4 in the feature register 0x0e) is set to 1, the keyscan is not returning a valid value. supply bypassing and wiring in order to achieve optimal performance the as1115 should be placed very close to the led display to minimize effects of electromagnetic inter f e rence and wiring inductance. furthermore, it is recommended to connect a 10f and a 0.1f ceramic capacitor between pins v dd and gnd to avoid power supply ripple ( s ee figure 27) . diode arrangement dig0 to dig7 seg a to g sep dp as1115 sda scl irq v dd i set sda irq gnd scl 2.7 to 5v 9.53k w p keya keyb sega segb segc segd seg e segf segg segdp irq diodes are optional and only required if multiple keystrokes must be detected simultaneously. if i2c self-addressing is used these two keys cannot be used for read- back and must be either hard wired opened or shorted. a short writes a logical 0 whereas an open writes a logical 1 as address bit. ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 21 25 as1115 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g s 10 package drawings and markings figure 29. qsop-24 marking fi gure 30. tqfn(4x4)-24 marking table 24. packaging code yy ww r / x zz last two digits of the current year manufacturing week plant identifier free choice / traceability code ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 22 25 as1115 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g s figure 31. qsop-24 package ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 23 25 as1115 datasheet p a c k a g e d r a w i n g s a n d m a r k i n g s figure 32. tqfn(4x4)-24 package ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 24 25 as1115 datasheet o r d e r i n g i n f o r m a t i o n 11 ordering information the devices are available as the standard products shown in t able 25 . no te: all products are rohs compliant and austriamicrosystems green. buy our products or get free samples online at icdirect: http://www.austriamicrosystems.com/icdirect technical support is found at http://www.austriamicrosystems.com/technicalsupport for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor table 25. ordering information ordering code marking description delivery form package as1115bsst as1115 64 leds, i2c interfaced led driver with keyscan tape and reel qsop24 as1115bqft as1115 tape and reel tqfn(4x4)24 ams ag technical content still valid
www.austriamicrosystems.com/leddriverics/as1115 revision 1.08 25 25 as1115 datasheet copyrights copyright ? 19972012, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austriaeurope. trademarks registered ?. a ll rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. a ustriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters a ustriamicrosystems ag tobelbaderstrasse 30 a8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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